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1/36 preliminary data september 2003 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m29f032d 32 mbit (4mb x8, uniform block) 5v supply flash memory features summary n supply voltage Cv cc = 5v 10% for program, erase and read operations n access time: 70 ns n programming time C 10s per byte typical n 64 uniform 64kbyte memory blocks n program/erase controller C embedded byte program algorithms n erase suspend and resume modes C read and program another block during erase suspend n unlock bypass program command C faster production/batch programming n temporary block unprotection mode n common flash interface C 64 bit security code n low power consumption C standby and automatic standby n 100,000 program/erase cycles per block n electronic signature C manufacturer code: 20h C device code: ach figure 1. packages tsop40 (n) 10 x 20mm
m29f032d 2/36 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. tsop connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 address inputs (a0-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 reset/block temporary unprotect (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 ready/busy output (rb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v cc supply voltage (5v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 block protection and blocks unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 2. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 read/reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 auto select command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 unlock bypass command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 unlock bypass program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 unlock bypass reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 chip erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 block erase command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 erase suspend command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 erase resume command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read cfi query command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 block protect and chip unprotect commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . 13
3/36 m29f032d status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 toggle bit (dq6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 alternative toggle bit (dq2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 table 8. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. reset/block temporary unprotect ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. tsop40 C 40 lead plastic thin small outline, 10 x 20mm, package outline . . . . . . . . 23 table 14. tsop40 C 40 lead plastic thin small outline, 10 x 20mm, package mechanical data . 23 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
m29f032d 4/36 block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 appendix a. block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. block addresses, m29f032d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 appendix b. common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 18. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 19. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 21. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 appendix c. block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23. programmer technique bus operations, byte = v ih or v il . . . . . . . . . . . . . . . . . . . . . 30 figure 14. programmer equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16. in-system equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 17. in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5/36 m29f032d summary description the m29f032d is a 32 mbit (4mb x8) non-volatile memory that can be read, erased and repro- grammed. these operations can be performed us- ing a single low voltage 5v supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the memory is divided into 64 uniform blocks of 64kbytes (see figure 5, block addresses) that can be erased independently so it is possible to preserve valid data while old data is erased. blocks can be protected in groups of 4 to prevent accidental program or erase commands from modifying the memory. program and erase com- mands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special op- erations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identi- fied. the command set required to control the memory is consistent with jedec standards. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is delivered with all the bits erased (set to 1). figure 2. logic diagram table 1. signal names ai05258 22 a0-a21 w dq0-dq7 v cc m29f032d e v ss 8 g rp rb a0-a21 address inputs dq0-dq7 data inputs/outputs e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output v cc supply voltage v ss ground nc not connected internally
m29f032d 6/36 figure 3. tsop connections a1 dq1 dq2 a10 a4 a2 a7 a6 a14 a20 a17 a18 dq7 a13 a19 a0 w dq5 dq3 v ss v cc dq4 dq6 a12 e rp a11 nc v cc ai05260 m29f032d 10 1 11 20 21 30 31 40 a3 a15 a16 g rb a8 a9 v ss dq0 a5 a21
7/36 m29f032d figure 4. block addresses note: also see appendix a, table 16 for a full listing of the block addresses. ai05259 64 kbyte 3fffffh 3f0000h 64 kbyte 01ffffh 010000h 64 kbyte 00ffffh 000000h m29f032d block addresses 3cffffh total of 64 64 kbyte blocks 64 kbyte 64 kbyte 3effffh 3e0000h 3dffffh 3d0000h 64 kbyte 020000h 02ffffh
m29f032d 8/36 signal descriptions see figure 2, logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a21). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data inputs/outputs (dq0-dq7). the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state ma- chine. chip enable (e ). the chip enable, e , activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g ). the output enable, g , con- trols the bus read operation of the memory. write enable (w ). the write enable, w , controls the bus write operation of the memorys com- mand interface. reset/block temporary unprotect (rp). the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 13 and figure 12, reset/ temporary unprotect ac characteristics for more details. holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . ready/busy output (rb ). the ready/busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations ready/busy is low, v ol . ready/busy is high-im- pedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy be- comes high-impedance. see table 13 and figure 12, reset/temporary unprotect ac characteris- tics. the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. v cc supply voltage (5v). v cc provides the power supply for all operations (read, program and erase). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply, see figure 10, ac measurement load cir- cuit. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . v ss ground. v ss is the reference for all voltage measurements.
9/36 m29f032d bus operations there are five standard bus operations that control the device. these are bus read, bus write, out- put disable, standby and automatic standby. see tables 2, bus operations, for a summary. typical- ly glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not af- fect bus operations. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 9, read mode ac waveforms, and table 10, read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figures 10 and 11, write ac waveforms, and tables 11 and 12, write ac characteristics, for details of the timing require- ments. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high-imped- ance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 9, dc characteristics. during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 300ns or more the memory enters automatic standby where the internal supply current is re- duced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. they require v id to be applied to some pins. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in tables 2, bus operations. block protection and blocks unprotection. blocks can be protected in groups of 4 against ac- cidental program or erase. see appendix a, table 16, block addresses, for details of which blocks must be protected together as a group. protected blocks can be unprotected to allow data to be changed. there are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. block protect and chip unprotect operations are described in appendix c. table 2. bus operations note: x = v il or v ih . operation e g w address inputs a0-a21 data inputs/outputs dq7-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih xhi-z standby v ih xxx hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih 20h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih ach
m29f032d 10/36 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. refer to table 3, commands, in conjunction with the following text descriptions. read/reset command. the read/reset com- mand returns the memory to its read mode where it behaves like a rom or eprom, unless other- wise stated. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, be- tween bus write cycles before the start of a pro- gram or erase operation, to return the device to read mode. once the program or erase operation has started the read/reset command is no longer accepted. the read/reset command will not abort an erase operation when issued while in erase suspend. auto select command. the auto select com- mand is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are re- quired to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until a read/reset command is issued. read cfi query and read/ reset commands are accepted in auto select mode, all other commands are ignored. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for stmicroelectronics is 20h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29f032d ach. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a12-a21 specifying the address of the block. the other address bits may be set to ei- ther v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0- dq7, otherwise 00h is output. program command. the program command can be used to program a value to one address in the memory array at a time. the command re- quires four bus write operations, the final write op- eration latches the address and data in the internal state machine and starts the program/erase con- troller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 4. bus read op- erations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. note that the program command cannot change a bit set at 0 back to 1. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from 0 to 1. unlock bypass command. the unlock bypass command is used in conjunction with the unlock bypass program command to program the memo- ry. when the cycle time to the device is long (as with some eprom programmers) considerable time saving can be made by using these com- mands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been is- sued the memory will only accept the unlock by- pass program command and the unlock bypass reset command. the memory can be read as if in read mode. unlock bypass program command. the un- lock bypass program command can be used to program one address in the memory array at a time. the command requires two bus write oper- ations, the final write operation latches the ad- dress and data in the internal state machine and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the pro- gram operation using the program command. a protected block cannot be programmed; the oper- ation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock by- pass mode. see the program command for details on the behavior. unlock bypass reset command. the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/reset
11/36 m29f032d command does not exit from unlock bypass mode. chip erase command. the chip erase com- mand can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation ap- pears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands, including the erase suspend com- mand. it is not possible to issue any command to abort the operation. typical chip erase times are given in table 4. all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see the sec- tion on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the chip erase command sets all of the bits in un- protected blocks of the memory to 1. all previous data is lost. block erase command. the block erase com- mand can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register sec- tion for details on how to identify if the program/ erase controller has started the block erase oper- ation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100s, leaving the data un- changed. no error condition is given when protect- ed blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend command. typical block erase times are given in table 4. all bus read operations during the block erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to 1. all previous data in the selected blocks is lost. erase suspend command. the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within 15s of the erase suspend command being is- sued. once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start im- mediately when the erase resume command is issued. it is not possible to select any further blocks to erase after the erase resume.
m29f032d 12/36 during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. read- ing from blocks that are being erased will output the status register. it is also possible to issue the auto select, read cfi query and unlock bypass commands during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be ac- cepted. erase resume command. the erase resume command must be used to restart the program/ erase controller after an erase suspend. the de- vice must be in read array mode before the re- sume command will be accepted. an erase can be suspended and resumed more than once. read cfi query command. the read cfi query command is used to read data from the common flash interface (cfi) memory area. this command is valid when the device is in the read array mode, or when the device is in autoselected mode. one bus write cycle is required to issue the read cfi query command. once the command is is- sued subsequent bus read operations read from the common flash interface memory area. the read/reset command must be issued to re- turn the device to the previous mode (the read ar- ray mode or autoselected mode). a second read/ reset command would be needed if the device is to be put in the read array mode from autoselect- ed mode. see appendix b, tables 17, 18, 19, 20, 21 and 22 for details on the information contained in the common flash interface (cfi) memory area. block protect and chip unprotect com- mands. groups of blocks can be protected against accidental program or erase. the protec- tion groups are shown in appendix a, table 16. the whole chip can be unprotected to allow the data inside the blocks to be changed. block protect and chip unprotect operations are described in appendix c. table 3. commands note: x dont care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal . command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2x a0papd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 read cfi query 1 55 98
13/36 m29f032d table 4. program, erase times and program, erase endurance cycles note: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. maximum value measured at worst case for both temperature and v cc after 100,000 program/erase cycles. 4. maximum value measured at worst case for both temperature and v cc . status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase sus- pend when an address within a block being erased is accessed. the bits in the status register are summarized in table 5, status register bits. data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the ad- dress just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts 0, the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. in erase suspend mode the data polling bit will output a 1 during a bus read operation within a block being erased. the data polling bit will change from a 0 to a 1 when the program/erase controller has suspended the erase operation. figure 5, data polling flowchart, gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has re- sponded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from 0 to 1 to 0, etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. if any attempt is made to erase a protected block, the operation is aborted, no error is signalled and dq6 toggles for approximately 100s. if any at- tempt is made to program a protected block or a suspended block, the operation is aborted, no er- ror is signalled and dq6 toggles for approximately 1s. figure 6, data toggle flowchart, gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to 1 when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to 0 back to 1 and attempting to do so will set dq5 to 1. a bus read operation to that ad- dress will show the bit is still 0. one of the erase parameter min ty p (1,2) max (2) unit chip erase 40 200 (3) s block erase (64 kbytes) 0.8 6 (4) s erase suspend latency time 30 s program (byte) 10 200 (3) s chip program (byte by byte) 40 200 (3) s program/erase cycles (per block) 100,000 cycles data retention 20 years
m29f032d 14/36 commands must be used to set all the bits in a block or in the whole memory from 0 to 1. erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing the erase timer bit is set to 1. before the program/erase controller starts the erase timer bit is set to 0 and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during erase operations. the al- ternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from 0 to 1 to 0, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to ad- dresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the er- ror. the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read opera- tions from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased cor- rectly. table 5. status register bits note: unspecified data bits should be ignored. operation address dq7 dq6 dq5 dq3 dq2 rb program any address dq7 toggle 0 C C 0 program during erase suspend any address dq7 toggle 0 C C 0 program error any address dq7 toggle 1 C C 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 C toggle 1 non-erasing block data read as normal 1 erase error good block address 0 toggle 1 1 no toggle 0 faulty block address 0 toggle 1 1 toggle 0
15/36 m29f032d figure 5. data polling flowchart figure 6. data toggle flowchart read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai05267 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq6 start read dq6 twice fail pass ai90195b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
m29f032d 16/36 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 6. absolute maximum ratings note: 1. minimum voltage may undershoot to C2v or overshoot to v cc +2v during transition for a maximum of 20ns. symbol parameter min max unit t bias temperature under bias C50 125 c t stg storage temperature C65 150 c v io input or output voltage (1) C0.6 v cc + 0.6 v v cc supply voltage C0.6 6 v v id identification voltage C0.6 13.5 v
17/36 m29f032d dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 7, operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 7. operating and ac measurement conditions figure 7. ac measurement i/o waveform figure 8. ac measurement load circuit table 8. device capacitance note: sampled only, not 100% tested. parameter m29f032d unit 70 min max v cc supply voltage 4.5 5.5 v ambient operating temperature C 40 85 c load capacitance (c l ) 100 pf input rise and fall times 10 ns input pulse voltages 0.45 to 2.4 v input and output timing ref. voltages 0.8 and 2.0 v ai05750 2.4v 0.45v 2.0v 0.8v ai05266 1.3v out c l c l includes jig capacitance 3.3k w 1n914 device under test v cc 0.1f symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
m29f032d 18/36 table 9. dc characteristics note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 20 ma i cc2 supply current (standby) ttl e = v ih 1ma i cc3 supply current (standby) cmos e = v cc 0.2v, rp = v cc 0.2v 150 a i cc4 (1) supply current (program/erase) program/erase controller active 20 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage ttl i oh = C2.5ma 2.4 v output high voltage cmos i oh = C100a v cc C 0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 a v lko (1) program/erase lockout supply voltage 3.2 4.2 v
19/36 m29f032d figure 9. read ac waveforms table 10. read ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter test condition m29f032d unit 70 t avav t rc address valid to next address valid e = v il , g = v il min 70 ns t avqv t acc address valid to output valid e = v il , g = v il max 70 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 ns t elqv t ce chip enable low to output valid g = v il max 70 ns t glqx (1) t olz output enable low to output transition e = v il min 0 ns t glqv t oe output enable low to output valid e = v il max 30 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 20 ns t ghqz (1) t df output enable high to output hi-z e = v il max 20 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 ns ai05261 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a21 g dq0-dq7 e telqv tehqx tghqz valid
m29f032d 20/36 figure 10. write ac waveforms, write enable controlled table 11. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. symbol alt parameter m29f032d unit 70 t avav t wc address valid to next address valid min 70 ns t elwl t cs chip enable low to write enable low min 0 ns t wlwh t wp write enable low to write enable high min 45 ns t dvwh t ds input valid to write enable high min 45 ns t whdx t dh write enable high to input transition min 0 ns t wheh t ch write enable high to chip enable high min 0 ns t whwl t wph write enable high to write enable low min 20 ns t av wl t as address valid to write enable low min 0 ns t wlax t ah write enable low to address transition min 45 ns t ghwl output enable high to write enable low min 0 ns t whgl t oeh write enable high to output enable low min 0 ns t whrl (1) t busy program/erase valid to rb low max 30 ns t vchel t vcs v cc high to chip enable low min 50 s ai05262 e g w a0-a21 dq0-dq7 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
21/36 m29f032d figure 11. write ac waveforms, chip enable controlled table 12. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. symbol alt parameter m29f032d unit 70 t avav t wc address valid to next address valid min 70 ns t wlel t ws write enable low to chip enable low min 0 ns t eleh t cp chip enable low to chip enable high min 45 ns t dveh t ds input valid to chip enable high min 45 ns t ehdx t dh chip enable high to input transition min 0 ns t ehwh t wh chip enable high to write enable high min 0 ns t ehel t cph chip enable high to chip enable low min 20 ns t av el t as address valid to chip enable low min 0 ns t elax t ah chip enable low to address transition min 45 ns t ghel output enable high chip enable low min 0 ns t ehgl t oeh chip enable high to output enable low min 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 ns t vchwl t vcs v cc high to write enable low min 50 s ai05263 e g w a0-a21 dq0-dq7 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
m29f032d 22/36 figure 12. reset/block temporary unprotect ac waveforms table 13. reset/block temporary unprotect ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter m29f032d unit 70 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 ns t plpx t rp rp pulse width min 500 ns t plyh (1) t ready rp low to read mode max 10 s t phphh (1) t vidr rp rise time to v id min 500 ns t vhh (1) v hh rise and fall time min 250 ns ai02931b rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl
23/36 m29f032d package mechanical figure 13. tsop40 C 40 lead plastic thin small outline, 10 x 20mm, package outline note: drawing is not to scale. table 14. tsop40 C 40 lead plastic thin small outline, 10 x 20mm, package mechanical data tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 b 0.170 0.270 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 d 19.800 20.200 0.7795 0.7953 d1 18.300 18.500 0.7205 0.7283 e 9.900 10.100 0.3898 0.3976 e 0.500 C C 0.0197 C C l 0.500 0.700 0.0197 0.0276 a 0 5 0 5 n40 40 cp 0.100 0.0039
m29f032d 24/36 part numbering table 15. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m29f032d 70 n 6 t device type m29 operating voltage f = v cc = 5v 10% device function 032d = 32 mbit (x8), uniform block speed 70 = 70 ns package n = tsop40: 10 x 20 mm temperature range 1 = 0 to 70 c 6 = C40 to 85 c option blank = standard packing t = tape & reel packing
25/36 m29f032d appendix a. block address table table 16. block addresses, m29f032d # size, kbyte address range protection group 63 64 3f0000h-3fffffh 15 62 64 3e0000h-3effffh 61 64 3d0000h-3dffffh 60 64 3c0000h-3cffffh 59 64 3b0000h-3bffffh 14 58 64 3a0000h-3affffh 57 64 390000h-39ffffh 56 64 380000h-18ffffh 55 64 370000h-37ffffh 13 54 64 360000h-36ffffh 53 64 350000h-35ffffh 52 64 340000h-34ffffh 51 64 330000h-33ffffh 12 50 64 320000h-32ffffh 49 64 310000h-31ffffh 48 64 300000h-30ffffh 47 64 2f0000h-2fffffh 11 46 64 2e0000h-2effffh 45 64 2d0000h-2dffffh 44 64 2c0000h-2cffffh 43 64 2b0000h-2bffffh 10 42 64 2a0000h-2affffh 41 64 290000h-29ffffh 40 64 280000h-28ffffh 39 64 270000h-27ffffh 9 38 64 260000h-26ffffh 37 64 250000h-25ffffh 36 64 240000h-24ffffh 35 64 230000h-23ffffh 8 34 64 220000h-22ffffh 33 64 210000h-21ffffh 32 64 200000h-20ffffh 31 64 1f0000h-1fffffh 7 30 64 1e0000h-1effffh 29 64 1d0000h-1dffffh 28 64 1c0000h-1cffffh 27 64 1b0000h-1bffffh 6 26 64 1a0000h-1affffh 25 64 190000h-19ffffh 24 64 180000h-18ffffh 23 64 170000h-17ffffh 5 22 64 160000h-16ffffh 21 64 150000h-15ffffh 20 64 140000h-14ffffh 19 64 130000h-13ffffh 4 18 64 120000h-12ffffh 17 64 110000h-11ffffh 16 64 100000h-10ffffh 15 64 0f0000h-0fffffh 3 14 64 0e0000h-0effffh 13 64 0d0000h-0dffffh 12 64 0c0000h-0cffffh 11 64 0b0000h-0bffffh 2 10 64 0a0000h-0affffh 9 64 090000h-09ffffh 8 64 080000h-08ffffh 7 64 070000h-07ffffh 1 6 64 060000h-06ffffh 5 64 050000h-05ffffh 4 64 040000h-04ffffh 3 64 030000h-03ffffh 0 2 64 020000h-02ffffh 1 64 010000h-01ffffh 0 64 000000h-00ffffh
m29f032d 26/36 appendix b. common flash interface (cfi) the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command is issued the de- vice enters cfi query mode and the data structure is read from the memory. tables 17, 18, 19, 20, 21 and 22 show the addresses used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 22, security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. issue a read command to return to read mode. table 17. query structure overview note: query data are always presented on the lowest order data outputs. table 18. cfi query identification string address sub-section name description 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout 40h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h security code area 64 bit unique device number address data description value 10h 51h "q" 11h 52h query unique ascii string "qry" "r" 12h 59h "y" 13h 02h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm amd compatible 14h 00h 15h 40h address for primary algorithm extended query table (see table 20) p = 40h 16h 00h 17h 00h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 00h 19h 00h address for alternate algorithm extended query table na 1ah 00h
27/36 m29f032d table 19. cfi query system interface information note: 1. not supported in the cfi address data description value 1bh 45h v cc logic supply minimum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 4.5v 1ch 55h v cc logic supply maximum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 5.5v 1dh 00h v pp [programming] supply minimum program/erase voltage 00h not supported na 1eh 00h v pp [programming] supply maximum program/erase voltage 00h not supported na 1fh 04h typical timeout per single byte program = 2 n s 16s 20h 00h typical timeout for minimum size write buffer program = 2 n s na 21h 0ah typical timeout per individual block erase = 2 n ms 1s 22h 00h typical timeout for full chip erase = 2 n ms see note (1) 23h 04h maximum timeout for byte program = 2 n times typical 256s 24h 00h maximum timeout for write buffer program = 2 n times typical na 25h 03h maximum timeout per individual block erase = 2 n times typical 8s 26h 00h maximum timeout for chip erase = 2 n times typical see note (1)
m29f032d 28/36 table 20. device geometry definition address data description value 27h 16h device size = 2 n in number of bytes 4 mbyte 28h 29h 00h 00h flash device interface code description x8 only async. 2ah 2bh 00h 00h maximum number of bytes in multi-byte program or page = 2 n na 2ch 01h number of erase block regions within the device. it specifies the number of regions within the device containing contiguous erase blocks of the same size. 1 2dh 2eh 3fh 00h region 1 information number of identical size erase block = 003fh+1 64 2fh 30h 00h 01h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte
29/36 m29f032d table 21. primary algorithm-specific extended query table table 22. security code area address data description value 40h 50h primary algorithm extended query table unique ascii string pri "p" 41h 52h "r" 42h 49h "i" 43h 31h major version number, ascii "1" 44h 30h minor version number, ascii "0" 45h 00h address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) yes 46h 02h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 04h block protection 00 = not supported, x = number of blocks per group 4 48h 01h temporary block unprotect 00 = not supported, 01 = supported yes 49h 04h block protect /unprotect 04 = m29w400b mode 4 4ah 00h simultaneous operations, 00 = not supported no 4bh 00h burst mode, 00 = not supported, 01 = supported no 4ch 00h page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word no address data description 61h xx 64 bit: unique device number 62h xx 63h xx 64h xx 65h xx 66h xx 67h xx 68h xx
m29f032d 30/36 appendix c. block protection block protection can be used to prevent any oper- ation from modifying the data stored in the memo- ry. the blocks are protected in groups, refer to appendix a, table 16 for details of the protection groups. once protected, program and erase op- erations within the protected group fail to change the data. there are three techniques that can be used to control block protection, these are the program- mer technique, the in-system technique and tem- porary unprotection. temporary unprotection is controlled by the reset/block temporary unpro- tection pin, rp ; this is described in the signal de- scriptions section. to protect the extended block issue the enter ex- tended block command and then use either the programmer or in-system technique. once pro- tected issue the exit extended block command to return to read mode. the extended block protec- tion is irreversible, once protected the protection cannot be undone. programmer technique the programmer technique uses high (v id ) volt- age levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a group of blocks follow the flowchart in figure 14, programmer equipment block protect flowchart. to unprotect the whole chip it is neces- sary to protect all of the groups first, then all groups can be unprotected at the same time. to unprotect the chip follow figure 15, programmer equipment chip unprotect flowchart. table 23, programmer technique bus operations, gives a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp . this can be achieved without violating the maximum ratings of the components on the micro- processor bus, therefore this technique is suitable for use after the memory has been fitted to the sys- tem. to protect a group of blocks follow the flowchart in figure 16, in-system block protect flowchart. to unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. to unprotect the chip follow figure 17, in-system chip unprotect flowchart. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the pro- cedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. table 23. programmer technique bus operations, byte = v ih or v il note: 1. block protection groups are shown in appendix a, table 16. operation e g w address inputs a0-a21 data inputs/outputs dq15aC1, dq14-dq0 block (group) protect (1) v il v id v il pulse a9 = v id , a12-a21 block address others = x x chip unprotect v id v id v il pulse a9 = v id , a12 = v ih , a15 = v ih others = x x block (group) protection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v il , a9 = v id , a12-a21 block address others = x pass = xx01h retry = xx00h block (group) unprotection verify v il v il v ih a0 = v il , a1=v ih , a6 = v ih , a9=v id , a12-a21 block address others = x retry = xx01h pass = xx00h
31/36 m29f032d figure 14. programmer equipment group protect flowchart note: block protection groups are shown in appendix a, table 16. address = group address ai05574 g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih , a0, a6 = v il , a1 = v ih a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
m29f032d 32/36 figure 15. programmer equipment chip unprotect flowchart note: block protection groups are shown in appendix a, table 16. protect all groups ai05575 a6, a12, a15 = v ih (1) e, g, a9 = v id data w = v ih e, g = v ih address = current group address a0 = v il , a1, a6 = v ih wait 10ms = 00h increment current group n = 0 current group = 0 wait 4s w = v il ++n = 1000 start yes yes no no last group yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
33/36 m29f032d figure 16. in-system equipment group protect flowchart note: block protection groups are shown in appendix a, table 16. ai05576 write 60h address = group address a0 = v il , a1 = v ih , a6 = v il n = 0 wait 100s write 40h address = group address a0 = v il , a1 = v ih , a6 = v il rp = v ih ++n = 25 start fail pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = group address a0 = v il , a1 = v ih , a6 = v il rp = v id issue read/reset command issue read/reset command write 60h address = group address a0 = v il , a1 = v ih , a6 = v il
m29f032d 34/36 figure 17. in-system equipment chip unprotect flowchart note: block protection groups are shown in appendix a, table 16. ai05577 write 60h any address with a0 = v il , a1 = v ih , a6 = v ih n = 0 current group = 0 wait 10ms write 40h address = current group address a0 = v il , a1 = v ih , a6 = v ih rp = v ih ++n = 1000 start fail pass yes no data = 00h yes no rp = v ih wait 4s read data address = current group address a0 = v il , a1 = v ih , a6 = v ih rp = v id issue read/reset command issue read/reset command protect all groups increment current group last group yes no write 60h any address with a0 = v il , a1 = v ih , a6 = v ih verify unprotect set-up end
35/36 m29f032d revision history table 24. document revision history date version revision details march-2001 -01 first issue (brief data) 21-jun-2001 -02 document expanded to full product preview 14-dec-2001 -03 55ns speed class removed, block protection appendix added, cfi table 21, address 2fh data clarified, read/reset operation during erase suspend clarified. 05-apr-2002 -04 description of ready/busy signal clarified (and figure 12 modified) clarified allowable commands during block erase clarified the mode the device returns to in the cfi read query command section 30-sep-2003 -05 notes 1 to 4 and erase suspend latency time and data retention parameters added in table 4, program, erase times and program, erase endurance cycles. figure 6, data toggle flowchart corrected. standard packing added in table 15, ordering information scheme.
m29f032d 36/36 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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